Bookcover of Low Power Wallace Multiplier
Booktitle:

Low Power Wallace Multiplier

A Design Prospective

LAP LAMBERT Academic Publishing (2020-03-01 )

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ISBN-13:

978-620-0-78341-7

ISBN-10:
6200783411
EAN:
9786200783417
Book language:
English
Blurb/Shorttext:
Multipliers are basic building blocks of many VLSI computational units. The performance of such VLSI circuits depends on the performance of multipliers. A multiplier is also one of the key hardware blocks in most digital signal processing (DSP) systems. Typical in DSP applications, where a multiplier plays an important role include digital filtering, digital communications and spectral analysis. Since multipliers are rather complex circuits and must typically operate at a high system clock rate, reducing the delay of a multiplier is an essential part of satisfying the overall design. So designing a fast multiplier is a challenging task for VLSI designers. There are various types of multipliers are available such as the array multiplier, carry-save multiplier, Wallace-tree multiplier, etc. Among this Wallace-tree multiplier or Wallace multiplier has been a very popular design due to its fast speed and low power. In this book, a design prospective of a low power Wallace Multiplier has been presented.
Publishing house:
LAP LAMBERT Academic Publishing
Website:
http://www.lap-publishing.com/
By (author) :
Inamul Hussain, Saurabh Choudhury, Manish Kumar
Number of pages:
64
Published on:
2020-03-01
Stock:
Available
Category:
Electronics, electro-technology, communications technology
Price:
4220.14 руб
Keywords:
Multiplier, low power VLSI, Wallace Multiplier, Digital Design

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